Field of the Invention
The invention relates to a method for fabricating semiconductor structures, in particular made of silicon carbide. The invention furthermore relates to a correspondingly fabricated semiconductor structure.
In the case of power semiconductor components, e.g. power MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor), particularly high requirements are made of the homogeneity, because many parts, referred to as cells, of these components are often connected in parallel and each cell should contribute the same proportion to a total current.
In the case of a vertical MOSFET cell with a so-called lateral channel region, which is known per se in the field of silicon technology, a so-called channel length is defined by the lateral overlap of a base region over a source region of the MOSFET with opposite conductivity types. In order to obtain a relatively low channel resistance, it has been tried to minimize the channel length of the MOSFET cell. Furthermore, mass production of components having at least approximately identical properties requires that the channel length is at least largely homogeneous across the entire wafer made of the semiconductor material and can be set in a reproducible manner from wafer to wafer.
A self-aligning method for fabricating vertical MOSFET components in silicon is disclosed in the book by "B. J. Baliga", Modern Power Devices, Krieger, Publishing Comp., 1992, pages 331-336. In the method described for the fabrication of a DMOS-FET (double-diffused MOSFET), first of all a MOS system (gate oxide and gate electrode) is prepared on a silicon layer of the n-conducting type, the silicon layer being produced by epitaxy. The MOS system is patterned photolithographically in the desired manner and forms a mask having defined cell windows for the subsequent implantation of boron ions. Afterwards, an auxiliary masking is applied, which, in each case in the center of the cell windows, masks a portion of the previously implanted p-doped base regions and thus keeps them accessible from the surface of the semiconductor structure. The mask system modified in this way serves as a mask for a further implantation step (usually with arsenic), which defines the n-doped source regions of the structure. The channel length of the structure results from the different diffusion coefficients of the slow donor and of the fast acceptor. The channel length can be set in a self-aligning manner by way of the temperature and duration of the annealing process. The MOS system is detrimentally affected only insignificantly, or not at all, by this high-temperature step. After the thermal annealing of the implanted dopants, an insulating oxide layer is applied to the structure. Contact windows are opened photolithographically in the oxide layer, in a manner aligned with the auxiliary masking. Finally, the surface is metalized. This method is noncritical with regard to the setting of the channel length. It requires just two relatively noncritical alignment steps in the case of the application of the auxiliary masking and the opening of the contact windows, but cannot be applied to semiconductors in which practically no diffusion takes place, such as e.g. SiC or diamond.
A method for fabricating a lateral MOSFET in silicon carbide of the 6H crystal type (6H--SiC) is described in the article "Self aligned 6H--SiC MOSFETs with improved current drive", J. N. Pan, J. A. Cooper, M. R. Melloch, Electronics letters, Jul. 6, 1995, Vol. 31, No. 14, pp. 1200-1201. In accordance with this method, adjacent windows in a mask plane define, within an epitaxially grown, p-doped 6H--SiC layer, in pairs, source and drain regions of a standard cell which are n-doped in each case through the use of the implantation of nitrogen ions.
However, since considerably higher temperatures (1200.degree. C.-1500.degree. C.) are necessary for SiC, in comparison with silicon (750.degree. C.-800.degree. C.), for annealing and activating the implanted dopants, the use of the MOS system as masking is problematic. In order not to damage the MOS system, a heat treatment can be effected only at temperatures of up to a maximum of 1200.degree. C. Moreover, the diffusion in SiC is negligibly small, with the result that there is no self-aligning control by way of a channel length in a manner corresponding to the silicon method. Consequently, implantation of acceptor ions is not possible. The channel length is set by way of the spacing of the windows in the mask, and the gate oxide and the gate electrode lie in a self-aligned manner above the inversion channel. The method cannot be applied to those types of components in which a channel region is implanted, because for this purpose p-type doping is necessary either for the source and drain or for the channel region. The maximum possible annealing temperature of 1200.degree. C. does not suffice, however, for annealing the lattice damage and activating the acceptor ions.
The fabrication of a nonplanar UMOS structure is described in the article "4H-Silicon Carbide Power Switching Devices" J. W. Palmour et al., Technical digest of International conference on SiC and related material, Kyoto, 1995, pp. 319-322. The source regions are defined by the implantation of donor ions into an epitaxially grown p-doped SiC layer. Through the use of reactive ion etching (RIE), aligned in each case with the center of the source regions, a U-shaped trench is opened in the surface of the semiconductor structure. The trenches in each case reach down into the n-doped SiC layer disposed under the p-doped SiC layer and accommodate gate oxide and gate electrode. The channel length is defined by the thickness of the p-doped SiC layer which remains in the vertical direction between the source region and the n-doped SiC layer. only a single implantation step is provided in this method as well. The channel length is controlled by way of the penetration depth of the nitrogen ions and the thickness of the p-doped SiC layer. A laterally disposed channel region cannot be realized by this method.
A further method for the self-aligned fabrication of a semiconductor structure in silicon with two implantation steps is presented in the article "A low loss/highly rugged IGBT-Generation--based on a self aligned process with double implanted n/n.sup.+ -Emitter", Proc. of the 6.sup.th international Symposium on power semiconductor devices & ICs, Davos, 1994, pages 171-175. The method is distinguished by the fact that after an implantation step, a spacer technique which is known in the silicon technology is employed. In a CVD process, the windows that have been previously etched into the mask plane are reduced in size, from their edge, uniformly by a defined amount of between 0.4 .mu.m and 0.6 .mu.m. With these windows that have been reduced in size, it is then possible, in a subsequent implantation step, to produce further semiconductor regions which are all precisely self-aligned, down to 0.3 .mu.m, with regard to respective semiconductor regions produced by the first implantation step. This described method has the disadvantage that it cannot be applied a number of times in succession, and the spacer technique allows the windows to be reduced in size only up to a maximum of 1 .mu.m. Moreover, deposition methods and a removal of the auxiliary layers are time-consuming and cost-intensive.